Performance analysis of N-type double gate junctionless transistor

Abstract

In this paper, the TCAD simulation of charge plasma based double gate junction-less transistor with channel length of 18nm is analyzed. The structure shows better ION/OFF ratio(107) compared to the conventional junction less transistors (JLT). The use of charge plasma concept for inducing n+-n+-n+ regions and generating free charge carrier for conduction makes the process of fabrication easier for the designed structure. The designed device since works at work-function value of 4.74eV, it reduces the constraints of using high gate metal work-function for JLTs. The substrate region is lightly and uniformly doped, which results in decreased random dopant fluctuation and hence results in less variation in threshold voltage of the device. The sensitivity of device to various parameter variations is investigated.