II-DFT: a hybrid dft architecture for low-cost high quality structural testing

Abstract

This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to industrial designs demonstrate significant savings in test cost in terms of test data volume and test application time without compromising test quality. Implementation of the HDFT architecture on Intel ASIC and microprocessor designs are described.