Design and fabrication of suspended high Q MIM capacitors by wafer level packaging technology

Abstract

A novel silicon-based suspended MIM capacitor fabrication technique combining thin-film and bulk silicon etching technologies with high-quality factor is presented. The influence of low resistive silicon on the parasitics of integrated capacitors is analyzed by EM simulation. The suspended structure is achieved and optimized by a two-step back-etching process. The Q factor of the 3.3 pF suspended MIM capacitor at 2 GHz is about 79% larger than the non-suspended one and the Qmax is increased from 46.8 to 61.9, respectively. And a ten-element π equivalent model including electrode and substrate parasitics as well as dielectric loss is used to fit the suspended MIM capacitors well up to 10 GHz, demonstrating that the suspended MIM capacitors exhibit both lower substrate loss and lower parasitic capacitance of the substrate.