Fail Bit Analysis System For Semiconductor Memory Wafers

S. Ishikawa, K. Ishihara, Y. Miyamot, I. Miyazki, T. Ohshikk, M. Sato
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引用次数: 5

Abstract

The fail bit data analysis system was developed to shorten the defect analysis time for semiconductor memory products. The system has the following features: (])Feature elicidation by display of wafer scale and detailed analysis by expansion function. (2)Display of fail bit distribution based on design data and transfer of coodinate data to SEM. (3)Data storage by data compression. 1 .Problem Areas in Fail Bit Analysis The analysis of fail bit distribution in semiconductor memory is effective in specifying structural defects in memory-mats and their surrounding circuits. For example,when the fail bits are in a line in the memory -mat as shown in Fig.], a problem in the data read circuit in the horizontal direction is clear.However,the following problems exist in actually implementing fail bit analysis. memory chip
半导体存储晶圆失效位分析系统
为了缩短半导体存储产品的缺陷分析时间,开发了失效位数据分析系统。该系统具有以下特点:(])通过晶圆刻度的显示进行特征提取,通过扩展功能进行详细分析。(2)根据设计数据显示失效位分布,并将坐标数据传输到SEM。(3)数据压缩存储。失效位分析中的问题区域分析半导体存储器中的失效位分布对于确定存储器垫及其周围电路的结构缺陷是有效的。例如,当故障位在存储器中排成一行(如图1所示)时,水平方向上的数据读取电路就明显存在问题。但在实际实施失效位分析时,存在以下问题。记忆体晶片
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