R. Grover, T. Acosta, C. AnDyke, E. Armagan, C. Auth, S. Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, G. Leatherman, S. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, P. Nayak, A. Neale, D. Nminibapiel, Benjamin Orr, J. Palmer, C. Pelto, S. Poon, I. Post, T. Pramanik, Anisur Rahman, S. Ramey, N. Seifert, K. Sethi, A. Schmitz, H. Wu, A. Yeoh
{"title":"A Reliability Overview of Intel’s 10+ Logic Technology","authors":"R. Grover, T. Acosta, C. AnDyke, E. Armagan, C. Auth, S. Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, G. Leatherman, S. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, P. Nayak, A. Neale, D. Nminibapiel, Benjamin Orr, J. Palmer, C. Pelto, S. Poon, I. Post, T. Pramanik, Anisur Rahman, S. Ramey, N. Seifert, K. Sethi, A. Schmitz, H. Wu, A. Yeoh","doi":"10.1109/IRPS45951.2020.9128345","DOIUrl":null,"url":null,"abstract":"We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS45951.2020.9128345","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.
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