Ties that bind [hardware description languages]

A. Crone
{"title":"Ties that bind [hardware description languages]","authors":"A. Crone","doi":"10.1049/ess:20060501","DOIUrl":null,"url":null,"abstract":"VHDL designers can take advantage of the advanced verification features of SystemVerilog thanks to the bind function in the newer language. One of the most important languages to emerge for advanced design and verification is SystemVerilog. This language offers a rich set of features for testbench automation, applying native assertions, functional coverage and constrained random test generation. These features make SystemVerilog increasingly appealing to VHDL users who have a number of verification-oriented features at their disposal but need to implement a more efficient functional verification methodology for complex designs.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronic Systems and Software","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/ess:20060501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

VHDL designers can take advantage of the advanced verification features of SystemVerilog thanks to the bind function in the newer language. One of the most important languages to emerge for advanced design and verification is SystemVerilog. This language offers a rich set of features for testbench automation, applying native assertions, functional coverage and constrained random test generation. These features make SystemVerilog increasingly appealing to VHDL users who have a number of verification-oriented features at their disposal but need to implement a more efficient functional verification methodology for complex designs.
绑定[硬件描述语言]的纽带
由于新语言中的绑定函数,VHDL设计人员可以利用SystemVerilog的高级验证功能。为高级设计和验证而出现的最重要的语言之一是SystemVerilog。这种语言为测试台架自动化提供了丰富的特性集,应用本机断言、功能覆盖和约束随机测试生成。这些特性使得SystemVerilog对VHDL用户越来越有吸引力,这些用户拥有许多面向验证的特性,但需要为复杂的设计实现更有效的功能验证方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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