Application of the Kull epilayer formulation to a compact model for junction diodes

Abstract

This paper presents an application of the Kull-Nagel epilayer formulation for conductivity modulation to a compact model for junction diodes. This enhancement allows for improved accuracy in modeling the bias-dependence of the series resistance, a critical figure of merit for diodes used in RF and switching applications. The model is implemented in Verilog-A as an extension to the 3-terminal electrothermal diode model presented in an earlier work [1]. Hardware-verified results are demonstrated for a 90nm SiGe BiCMOS technology featuring an integrated PIN diode.