{"title":"A Fully Integrated 1.2V LDO Regulator","authors":"K. Abugharbieh, Basel Yaseen, Abdullah Deeb","doi":"10.1109/ICM50269.2020.9331816","DOIUrl":null,"url":null,"abstract":"This work presents a fully integrated low-drop out voltage regulator that achieves a fast-transient response by utilizing two feedback mechanisms. The first feedback mechanism is an analog regulation that includes an error amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS based or a PMOS based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, sharp changes in load current is addressed by high-speed current DACs and is not limited by the performance of the error amplifier. The LDO was implemented using 180nm CMOS technology devices. It uses a supply voltage input range of 1.6 V – 2.0 V and produces an output voltage of 1.2 V. In simulations, the LDO regulator achieves 188 uA quiescent current, -56 dB PSRR @ 1 KHz noise frequency and an output voltage drop of around 200 mV for a load current step of 100 mA.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 32nd International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM50269.2020.9331816","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This work presents a fully integrated low-drop out voltage regulator that achieves a fast-transient response by utilizing two feedback mechanisms. The first feedback mechanism is an analog regulation that includes an error amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS based or a PMOS based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, sharp changes in load current is addressed by high-speed current DACs and is not limited by the performance of the error amplifier. The LDO was implemented using 180nm CMOS technology devices. It uses a supply voltage input range of 1.6 V – 2.0 V and produces an output voltage of 1.2 V. In simulations, the LDO regulator achieves 188 uA quiescent current, -56 dB PSRR @ 1 KHz noise frequency and an output voltage drop of around 200 mV for a load current step of 100 mA.