Logic verification of very large circuits using Shark

Abstract

In this paper, we will present Shark, a software based logic verification technology that allows high-performance switch-level simulation of multi-million transistor circuits on general-purpose workstations. Shark achieves high-performance simulations on very large circuits through three key technologies: 1) a circuit partitioner based on latch boundary components, design hierarchy driven clustering, and latch/activity load balancing, 2) a high-performance switch-level simulator capable of simulating very large models and run word-parallel simulations, and 3) a simulation backplane that can connect any number of simulators to form a distributed/parallel simulation environment. Shark has been tested on circuits of up to 15 M transistors. On an Intel circuit with about 5 M transistors, Shark achieved a simulation throughput of 19 Hz.