Slow trap profiling-a new technique for characterising slow traps in MOS dielectrics

Abstract

The authors present a new technique for characterising slow traps in MOS structures which has several important advantages over existing measurement techniques. By stepping the gate voltage of a MOS capacitor and recording the resultant current transients, a slow trap profile can be generated that simultaneously shows the trap densities and their response times at various voltages, even in the strong inversion region. Results are shown for the case of a device damaged by plasma etching and comparisons made with the commonly used quasi-static C-V technique.