Parasitic resistance and leakage reduction by raised source / drain extention fabricated with cluster ion implantation and millisecond annealing

Abstract

We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B18H22) implantation and high-temperature millisecond annealing processes and a facet-structure-control of the RSDext of less than 10 nm thickness for suppressing a fringe capacitance increase for the “effective” ultra-shallower junction formation. As the results, experimentally obtained our pMOSFETs with raised source/drain extension show almost the same LMIN, 1/2 times lower parasitic resistance and lower junction leakage.