Sensitive Devices and Phase Noise Degradation Mechanisms on all-NMOSFET RF VCO Aging

S. Pazos, Juan J. Baudino, Matías N. Joglar, F. Aguirre, C. Navarro, F. Palumbo, F. Silveira
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Abstract

Device level reliability is introduced into simulations of an optimized all-NMOSFET, cross-coupled, radiofrequency Voltage Controlled Oscillator to trace the sensitive devices and parameters that reduce circuit performance over time. Parametric DC time dependent degradation is considered in all the devices of the circuit along with correlated flicker and thermal noise increase under hot carrier injection stress. Results show that, rather than the changes introduced by stress on DC parameters, the proposed topology is very sensitive to device level noise increase due to stress-induced traps, particularly at early stages of circuit life. This highlights the requirement of a unified simulation framework that takes into account not only DC/AC small signal degradation models but also device noise degradation in noise sensitive circuits.
全nmosfet射频VCO老化的敏感器件和相位噪声衰减机制
将器件级可靠性引入到优化的全nmosfet,交叉耦合,射频压控振荡器的仿真中,以跟踪随时间降低电路性能的敏感器件和参数。在热载流子注入应力下,电路中所有器件均考虑了参数化直流时变退化以及相关闪烁和热噪声的增加。结果表明,与应力对直流参数的影响不同,所提出的拓扑结构对由于应力诱导陷阱引起的器件级噪声增加非常敏感,特别是在电路寿命的早期阶段。这突出了对统一仿真框架的要求,该框架不仅要考虑DC/AC小信号退化模型,还要考虑噪声敏感电路中的器件噪声退化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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