Reducing conflicts in SMT VLIW processor for higher throughput

Abstract

Cache misses and insufficient instruction-level parallelism (ILP) in a single program make functional units of VLIW (very long instruction word) processor underused. Simultaneous multithreading (SMT) technology is one of the best choices to improve the utilization of functional units in processors, since it can convert thread-level parallelism (TLP) to ILP. Previous work investigate how to incorporate SMT technology with VLIW processors, but none of them reveals further what prevents SMT VLIW processors from achieving higher throughput. In addition, those methods that enhance throughputs for SMT superscalar processors are unsuitable for VLIW processors. In this paper, we propose an approach, which reduces conflicts among threads with moderate hardware costs, to improve the utilization of functional units. Experimental results show that our approach can effectively increase throughputs of SMT VLIW processors.