A 2 GHz clock direct frequency synthesiser

Abstract

Digital to Analogue Converters (DACs) which each have a faster operating specification than any DAC currently available, The circuit is composed of a number of structured circuit blocks, each of which can be tested independently. This approach has benefits both during device evaluation and as an aid to minimising production test times. Inucduction A block diagram of a direct frequency synthesiser is shown in figure 1. The main operational difference between a direct frequency synthesiser and the Phase Locked Loop (PLL) type is that the DFS does not contain feedback loops. This is a major advantage in settling to a new frequency; a good PLL has acquisition times of amund Ims, whereas the DFS can acquire a new frequency in a time limited only by pipeline delays in the accumulator and the DAC settling time. The frequency shift in the DFS is phase coherent, which is very difficult to achieve in any other way. The primary source of stability is the clock oscillator, so that, in the limit, since the clock is always at a higher frequency than the output, the output phase noise is better than the clock itself.