Exploring Optimum Designs for 1.2kV 4H-SiC JBS Diode Integrated MOSFETs (JBSFETs)

Stephen A. Mancini, Seung Yup Jang, Dongyoung Kim, Woongje Sung
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Abstract

Several different designs of 1.2kV-rated 4H-SiC JBS diode integrated MOSFETs (JBSFETs) have been successfully fabricated to increase the 3rd quadrant device performance while maintaining the electrical characteristics on both the forward and blocking modes of operation when compared to its MOSFET counterpart. Incorporating the Schottky area in an efficient manner to improve overall device performance has been a critical path in the development and adoption of 4H-SiC JBSFETs rather than MOSFETs co-packaged with JBS Diodes. Device design, fabrication, and electrical performances are discussed in this paper and as a result, an optimum JBSFET design is proposed.
1.2kV 4H-SiC JBS二极管集成mosfet (jbsfet)优化设计探索
几种不同设计的额定电压为1.2 kv的4H-SiC JBS二极管集成MOSFET (jbsfet)已经成功制造,以提高第三象限器件的性能,同时与MOSFET相比,保持前进和阻断工作模式的电气特性。以有效的方式整合肖特基区以提高整体器件性能是开发和采用4H-SiC jbsfet而不是与JBS二极管共封装的mosfet的关键途径。本文讨论了器件的设计、制造和电学性能,从而提出了一种最佳的jbset设计方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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