{"title":"A digital controlled solar array regulator employing the charge control","authors":"Y. Cho, B. Cho","doi":"10.1109/IECEC.1997.658213","DOIUrl":null,"url":null,"abstract":"A microprocessor controlled solar array regulator (SAR) system is presented. The inner analog loops employing the charge current control scheme continuously regulate the solar array output power according to the reference value generated by the electrical control unit (ECU). The ECU consists of peak power tracking and a battery charge current regulation algorithm. Modeling, analysis and a design procedure of the inner loops and the system loop are presented, taking into account the interaction between the inner analog loops and the outer digital loops. Utilizing the inherent characteristics of the inner voltage and current loops, the system's dynamic performance and stability can be optimized up to the speed limit of the microprocessor.","PeriodicalId":183668,"journal":{"name":"IECEC-97 Proceedings of the Thirty-Second Intersociety Energy Conversion Engineering Conference (Cat. No.97CH6203)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IECEC-97 Proceedings of the Thirty-Second Intersociety Energy Conversion Engineering Conference (Cat. No.97CH6203)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECEC.1997.658213","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A microprocessor controlled solar array regulator (SAR) system is presented. The inner analog loops employing the charge current control scheme continuously regulate the solar array output power according to the reference value generated by the electrical control unit (ECU). The ECU consists of peak power tracking and a battery charge current regulation algorithm. Modeling, analysis and a design procedure of the inner loops and the system loop are presented, taking into account the interaction between the inner analog loops and the outer digital loops. Utilizing the inherent characteristics of the inner voltage and current loops, the system's dynamic performance and stability can be optimized up to the speed limit of the microprocessor.