The power7TM processor SoC

D. Wendel, R. Kalla, J. Friedrich, J. Kahle, J. Leenstra, C. Lichtenau, B. Sinharoy, William J. Starke, V. Zyuban
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引用次数: 3

Abstract

Introducing POWER7TM the latest member of the IBM POWERTM processor family. A 567mm² chip implemented in 45nm SOI technology, holding eight quad threaded cores, a 32MB shared eDRAM L3, two memory controllers and high bandwidth SMP interfaces. The new out of order, shallow pipeline core with 12 execution units, multiport L1 caches and a private 256kB L2 offers the efficiency to support 4x the number of cores within the same power envelope as its predecessor. Supporting over 4GHz, the L1 data cache loop is kept to 2 cycles. Data from the L2 can be returned to the core at a rate of 32B per cycle.
power7TM处理器SoC
介绍IBM POWERTM处理器家族的最新成员POWER7TM。采用45nm SOI技术的567mm²芯片,拥有8个四线程内核,32MB共享eDRAM L3,两个内存控制器和高带宽SMP接口。新的无序浅管道内核具有12个执行单元,多端口L1缓存和专用256kB L2,在相同的功率范围内,其效率可以支持4倍于其前身的内核数量。支持超过4GHz, L1数据缓存循环保持在2个周期。来自L2的数据可以以每个周期32B的速率返回到核心。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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