Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study

Abstract

3D-LSI chip containing through-silicon-via (TSV, diameters ranging from 5 μm to 30 μm) with two different dielectric liners has been investigated for thermo-mechanical stress (TMS) in Si via micro-Raman spectroscopy and micro-X-ray diffraction analysis. Both the micro-Raman and micro-X-ray diffraction results revealed that the low-k CVD-grown dielectric polyimide (PI) liner tremendously reduces the TMS in the vicinal Si as well as the Si sandwiched between TSVs. It can be explained that the observed smaller TMS values for TSVs with PI is owing to the partial accommodation of the expanded Cu during thermal cycling by the low modulus, soft PI.