The likelihood of multiple bit-flips due to neutron strikes and its implications on circuit designs

Abstract

A soft error is typically modeled as a probabilistic single bit-flip model. In such models, an important issue to consider is the likelihood of multiple errors. The fact that a particle strike causes multiple flips is noted in the literature. We use post-layout circuit simulations to characterize the impact of a single event transient (SET) on logic circuits and quantify the likelihood of multiple flips. We find that the impact of an SET needs to be viewed across two clock cycles and a good fraction of errors had multiple register flips. A key observation is that, amongst the erroneous outcomes, the probability of multiple flips for ‘gate-strike’ cases was substantial and went up to 50%, where as those for ‘register-strike’ cases was only 2%. This implies that, even if we were to eliminate the flips due to register strikes using robust flip-flop designs, a large fraction of the remaining flips (due to gate strikes) is likely to be multiple flips. Further, when a strike affected two nearby transistors, we saw an increase of a factor of 2x in multiple flip probability. It is also likely that two SETs merge to produce a wider SET, thus increasing its probability of getting captured. This implies that, existing fault tolerant latch designs may need to be revisited to handle such scenarios.