Timing requirement for reliable latch-based circuit design

Abstract

This paper presents a framework of simulation and verification methodology for latch-based VLSI design. The proposed methodology includes optimal latch insertion point identification, how to consider clock skew for timing, and how to simulate circuits to verify the timing and functionality considering the clock skew in high speed VLSI systems for latch-based design. An existing flip-flop based FFT block is converted to latch-based design using the proposed methodology, and the performance of the block is increased by 10%.