The influence of the gate trench orientation to the crystal plane on the conduction properties of vertical GaN MISFETs for laser driving applications

Abstract

Vertical GaN based MISFETs for high voltage power switching applications have the potential to outperform Si and SiC based competitors in terms of power density and switching speed [1] – [3] . In this work the development of vertical GaN MISFET technology is focused on pulsed laser driving applications with maximum voltages < 100 V ( Fig. 1 ). Drivers for pulsed lasers are required to deliver very high currents up to 250 A in very short pulse lengths of 3 ns to 10 ns [4] . Vertical GaN MISFETs are in particular suited for realizing the required very steep current slopes due to their low output capacitance and gate charge figure of merits, C OSS × R ON and Q G * R ON . Further, the vertical GaN transistor topology enables a compact assembly of the laser diode die directly on top of the GaN transistor die to achieve an ultimately small current loop inductance ( Fig. 1 ) in the laser drive circuit. Additionally, the vertical device concept allows aggressive device scaling and enables a high current density per unit area [5] . On the other hand, the channel conductivity under inversion conditions may be compromised by high insulator channel interface defect density. This would result in low mobility and low carrier density. In this work devices with different gate trench orientation to the a- and m- GaN lattice planes grown on ammono-thermal substrate [8] are studied. Fig. 2 explains the location of the respective planes in the lattice and the convention of crystal cut to identify them on the wafer. Recently, it was demonstrated that devices grown on sapphire and on Si substrates with gate trench parallel to the GaN m -plane have superior conduction properties [6] – [7] ; however this is in contradiction to our finding. The epitaxial layers are grown by MOVPE. The epitaxial stack consists of 3.2 gm n + -GaN drain substrate contact layer, 5.3 gm n - -GaN (1.4 × 10 17 cm -3 ) drift layer, 300 nm p -GaN (1.5 × 10 17 cm -3 ) blocking layer followed by 500 nm n -GaN (1 × 10 18 cm -3 ) source cap [5] . The device process sequence follows the "ohmic contacts first" concept. For simplifying electrical characterization an additional top side drain ohmic contact is formed on the wafer front side along with the source ohmic contact in a coplanar pad configuration. Next a 25 nm Al 2 O 3 gate insulator is deposited by PEALD on the opened trench sidewall. The gate electrode consists of a sputtered TiW film reinforced with electroplated Au. For electrical evaluation two similar devices types with gate trenches parallel to the crystal m -plane and a -plane are measured. The transistors have a hexagonal cell design with the same gate width of 32.0 mm and ~305 mm / mm 2 gate density ( Fig. 3 ). The devices are electrically characterized using simultaneous 200 μs gate and drain pulses. Fig. 4 summarizes the wafer level median bidirectional sweep transfer and output characteristics of the vertical GaN MISFETs measured on the two devices types. While the m -plane devices show a median maximum current density of ~1100 A/cm 2 , the a -plane devices show a median of more than 4000 A/cm 2 . The evaluated threshold voltage and specific ON-state resistance are [6.3 ± 0.4 V, 2.2 ± 0.2 mΩcm 2 ] and [4.3 ± 0.2 V, 1.1 ± 0.1 mΩcm 2 ] for m- and a -plane devices respectively. The gate current for all devices is below the detection limit of 0.1 μA. Fig. 5 shows a summary of the wafer level R ON as a function of the reciprocal gate width, W G . From the fittings the average intrinsic channel sheet resistance, ${\bar R_{{\text{S}}{{\text{h}}_ - }{\text{ch}}}}$ , and the sum of the extrinsic series resistances, $\sum {{{\bar R}_{{\text{ext}}}}} $ , are evaluated [5] . It is shown that the channel intrinsic sheet resistance is primarily responsible for the difference between the two types of devices. Since for both device types epitaxial layers, process and the geometrical dimensions are identical, the extrinsic resistances are nearly identical. Thus devices with gate trench parallel to the a -plane are chosen for the laser driver due to their superior conduction properties. For the electro-optical characterization a laser pulsing test module has been realized on an AlN ceramic board ( Fig. 6 .). It consists of a GaAs based broad area DBR diode laser with an aperture of 50 μm and a cavity length of 3 mm. The laser is mounted on top of the vertical GaN MISFET using CuW interposer and fits quite well to the GaN chip dimensions - laser current aperture and active transistor area are matching properly. Furthermore, ceramic block capacitors which temporarily deliver the energy for the short laser pulses are placed close-by in order to achieve minimum loop inductance. An electrical circuit drives the GaN MIS-FET. The whole arrangement has been tested and demonstrated laser pulses with a pulse width of 3.6 ns at a repetition rate of 500 kHz, see Fig. 7 . The optical peak power was about 4 W. Fig. 7 also shows the emission wavelength at about 905 nm at different excitation levels.