High speed 15 ns 4 Mbit SRAM for space application

Abstract

A high speed 15 ns 4 Mbit asynchronous SRAM, 500 /spl mu/A stand-by current, 300 krad total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6 V, and ambient temperature from -55 to +125/spl deg/C. A high density die size of 68.3 mm/sup 2/ allows the use of a specific 36-pins dual in line flat pack package with a 500 mil width, making this product very competitive against SEU hardened chips. Successful silicon results are presented as well as radiation tests up to 300 krad.