S. Pazos, F. Aguirre, E. Romero, G. Peretti, S. Verrastro
{"title":"TRAM applied to second-order active filter designed in CMOS technology","authors":"S. Pazos, F. Aguirre, E. Romero, G. Peretti, S. Verrastro","doi":"10.1109/EAMTA.2015.7237378","DOIUrl":null,"url":null,"abstract":"The ability of TRAM for detecting parametric faults in a second-order filter selected as a case of study is studied in this work. Particularly, we adopt a low-pass Sallen-Key filter synthesized on a 500nm CMOS technology. We perform the design using diffused resistors, poly-poly capacitors and a full-custom operational amplifier. For fault injection and simulation, we adopt a previously reported fault model. Different combinations of test parameters are evaluated in this paper with the aim of determining the tradeoff between fault coverage and complexity of the test. Our results show that the simultaneous monitoring of peak time and overshoot gives reasonable fault coverage. The monitoring of other test parameters causes (in some cases) an improvement that should be considered as marginal.","PeriodicalId":101792,"journal":{"name":"2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EAMTA.2015.7237378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The ability of TRAM for detecting parametric faults in a second-order filter selected as a case of study is studied in this work. Particularly, we adopt a low-pass Sallen-Key filter synthesized on a 500nm CMOS technology. We perform the design using diffused resistors, poly-poly capacitors and a full-custom operational amplifier. For fault injection and simulation, we adopt a previously reported fault model. Different combinations of test parameters are evaluated in this paper with the aim of determining the tradeoff between fault coverage and complexity of the test. Our results show that the simultaneous monitoring of peak time and overshoot gives reasonable fault coverage. The monitoring of other test parameters causes (in some cases) an improvement that should be considered as marginal.