An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Abstract

This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap biass-witching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.