{"title":"HD 180 FPS FPGA Processor to Generate Depth Image with Clear Object Boundary","authors":"M. Miyama","doi":"10.1109/ISDCS.2019.8719096","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel fast method of depth image generation with super-pixels (SPs) that introduces a matching algorithm on SP basis, one-way check using only unidirectional disparities, and a cost filter on SP basis. In architecture design, an SP segmentation circuit that performs four iterations for whole image in one pass with four processing elements (PEs) is introduced. An SP-based stereo matching circuit is configured by serially connecting the same number of PEs as the maximum disparity, and performs parallel matching of all disparities for a left pixel, while suppressing memory access of the right pixel to 1 pixel / cycle. We implemented an FPGA processor with OpenCL and achieved high throughput of HD 180 fps with a disparity range of 192 pixels.","PeriodicalId":293660,"journal":{"name":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISDCS.2019.8719096","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes a novel fast method of depth image generation with super-pixels (SPs) that introduces a matching algorithm on SP basis, one-way check using only unidirectional disparities, and a cost filter on SP basis. In architecture design, an SP segmentation circuit that performs four iterations for whole image in one pass with four processing elements (PEs) is introduced. An SP-based stereo matching circuit is configured by serially connecting the same number of PEs as the maximum disparity, and performs parallel matching of all disparities for a left pixel, while suppressing memory access of the right pixel to 1 pixel / cycle. We implemented an FPGA processor with OpenCL and achieved high throughput of HD 180 fps with a disparity range of 192 pixels.