A 50 ns/15 V alterable n-channel nonvolatile memory device

Abstract

A new structure for a Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) is described. The new structure uses a modification of the previously reported FCAT (FCAT-I). The key improvement is that the floating gate couples better with the control gate. This device can oprate in both write and erase modes under high speed ( ≥ 50 ns( and low voltage ( ≤ 15 V) condition. Another useful feature is the saturation of the high level thresold voltage independent of write pulse widhs greater than 50 ns.