Influence of Process-Voltage-Temperature variations on the behavior of a hybrid SET-FET circuit

Abstract

This contribution studies the improvements, in terms of performance and variability tolerance, of implementing an hybrid CMOS-SET device when different Field Effect Transistors are regarded, e.g. Nanowire, UTBB FDSOI and FinFET. The Nanowire-based SET-FET presents the highest integration level and a significant increase of drive current and variability mitigation. Moreover, the SET-FET implementation based on UTBB FDSOI allows the use of body-bias voltage and it permits to manage dynamically and more accurately the whole device response.