A design project for system design with systemC

Abstract

In this paper, we propose a co-simulation project involving design of a heterogeneous system based on an 8-bit RISC processor, which could be used to demonstrate system level design. A system, being a heterogeneous environment involves hardware and software modules, with communication involved between the modules. Because system architects and software engineers commonly use C/C++, we demonstrate the use of SystemC, a C++ class library to model the hardware functionality in the system, thus providing a smoother design flow in such an environment. Replacing the traditional hardware description languages (HDLs) with SystemC minimizes the communication overheads involved in current system design flow, decreases simulation time and thus speeds up the design process.