Customized Routing Optimization Flow to Fix Timing Violations in Ultra Deep Sub Micron Technology

Abstract

In ultra-deep sub-micron technology, Routing has become challenging due to ever increasing number of metal layers, distinct layer thicknesses, new design rules and design complexity. Due to increase in congestion with lower technology nodes designer has to predict during floor plan weather routing is possible with meeting timing requirements. It is not enough to route only but need to route with DRC clean and without degrading post layout timings. Area reduction with lower node technology, routing congestion increases on chip and in that scenario need to route the best topology with metal layers. This article will discuss about routing a net with different routing topologies and the best topology which meets timing and DRC requirements will be routed. Flow is developed which will select the best topology from available topologies on the basis of different criteria and net will be routed automatically with given metal layers. Once it is routed, It will also fix the timing violations on the net with different layout solutions.