Circuit partitioning for waveform relaxation

Abstract

New partitioning strategies for the simulation of bipolar circuits using the waveform relaxation method are presented. On the one hand concepts known from layout-generation and node tearing simulation are used. On the other hand the hierarchical structure of the circuit description list and a minimal-cut criterion is used to find a good partitioning. With the help of these new partitioning algorithms it is possible for the first time to simulate large bipolar circuits using waveform relaxation. The applicability of the algorithms is demonstrated by the simulation of real-life circuits.<>