Performance enhancement of a subthreshold MOS folded-cascode OTA using enhanced lateral BJT input stage

Abstract

An enhanced lateral BJT in an n-well CMOS technology is formed by connecting a PMOS and a lateral pnp BJT in parallel. In the weak inversion, it offers us an exponential pMOS device with a slope factor of unity implying that its transconductance has been enhanced. This paper applies the enhanced lateral pnp BJTs to realizing a differential pair input stage for a folded-cascoded OTA to obtain better analog performance compared with the conventional folded-cascoded OTA. Verified by circuit simulation in 0.18-μm CMOS process environments for the same values of dc bias current and physical dimensions, the OTA with the enhanced input stage achieves more than 30% improvement in terms of dc gain, unity-gain frequency and input-referred noise.