Power-down synthesis for analog circuits including switch sizing

Abstract

In order to reduce the power consumption of a system-on-chip, analog circuits can be switched off when not needed with the help of power-down switches. The power-down synthesis task comprises the structural synthesis of the power-down circuitry and switch sizing. A first approach for automatic structural synthesis was published recently. This paper completes the power-down synthesis task by an effective, efficient and very easy sizing heuristic. An optimum size for the power-down switches is identified. The sizing approach is derived from exhaustive simulation results for three different amplifier circuits and a voltage-controlled ring oscillator. The variations in the power-on performance values, the power consumption during power-down mode, the power-on to power-down settling time and the power-down to power-on settling time are determined for different sizes of the power-down switches. From the simulation results, it can be concluded that the technology's minimal switch size can be chosen for the switches. This simple sizing step completes state-of-the-art power-down synthesis with the missing sizing step.