A High Gain Amplifier Design for Neural Signal Acquisition

Abstract

This paper delineates a simulated neural signal amplifier with a very high gain and enhanced supply rejection along with low noise operation. We describe a micro-power complementary metal-oxide-semiconductor (CMOS) design. The amplifier comprises of two stages and at the input juncture, the differential pair is used to attain an optimum input-referred noise. The amplifier is outlined in a typical 180-nm CMOS process using cadence tool. The design yields a midband gain of 70.0 dB with an input-referred noise of 4.33 µVrms and frequency from 320 mHz to 9.0 kHz is selected as - 3 dB bandwidth while it consumes 6.16 µW from a 1.8 V supply, resulting in a noise efficiency factor of 3.25. The power supply rejection ratio of 133.5 dB has been recorded in the passband.