A 1.2V 84dB 8mW time-interleaved sample and hold circuit in 90 nm CMOS

Abstract

This paper reports design, efficiency and measurement results of time interleaved sample and hold circuit based on closed loop switched capacitor technique. The prototype sample and hold with 84 dB dynamic range at 120 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 8 mW at 1.2 V power supply and measures 0.22 mm2.