{"title":"2D Ferroelectric $\\pmb{\\mathrm{CuInP}_{2}\\mathrm{S}_{6}}$: Synthesis, ReRAM, and FeRAM","authors":"Pai-Ying Liao, M. Si, G. Qiu, P. Ye","doi":"10.1109/DRC.2018.8442257","DOIUrl":null,"url":null,"abstract":"2D ferroelectric-gated field-effect transistors are promising for future non-volatile memory and low-power logic applications, to combine the advantage of both 2D semiconductors and ferroelectric insulators [1]–[3]. However, the non-ideal 2D semiconductor/3D insulator interface results in interface traps which degrade the device performance, variability and reliability. To integrate 2D semiconductor together with 2D ferroelectric insulator as 2D van der Waals heterostructure ferroelectric field-effect transistors (Fe-FETs) can eliminate the interface trap issue and achieve ideal insulator/semiconductor interface in principle. Copper indium thiophosphate $(\\mathrm{CuInP}_{2}\\mathrm{S}_{6}$, CIPS) is a novel two-dimensional (2D) ferroelectric material with layered single crystal structure and decent ambient stability [4]–[6]. Furthermore, it illustrates not only clear room temperature ferroelectric property with Curie point around 315 K, but also ferroelectric resistive switching characteristic.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 76th Device Research Conference (DRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2018.8442257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
2D ferroelectric-gated field-effect transistors are promising for future non-volatile memory and low-power logic applications, to combine the advantage of both 2D semiconductors and ferroelectric insulators [1]–[3]. However, the non-ideal 2D semiconductor/3D insulator interface results in interface traps which degrade the device performance, variability and reliability. To integrate 2D semiconductor together with 2D ferroelectric insulator as 2D van der Waals heterostructure ferroelectric field-effect transistors (Fe-FETs) can eliminate the interface trap issue and achieve ideal insulator/semiconductor interface in principle. Copper indium thiophosphate $(\mathrm{CuInP}_{2}\mathrm{S}_{6}$, CIPS) is a novel two-dimensional (2D) ferroelectric material with layered single crystal structure and decent ambient stability [4]–[6]. Furthermore, it illustrates not only clear room temperature ferroelectric property with Curie point around 315 K, but also ferroelectric resistive switching characteristic.