2D Ferroelectric $\pmb{\mathrm{CuInP}_{2}\mathrm{S}_{6}}$: Synthesis, ReRAM, and FeRAM

Pai-Ying Liao, M. Si, G. Qiu, P. Ye
{"title":"2D Ferroelectric $\\pmb{\\mathrm{CuInP}_{2}\\mathrm{S}_{6}}$: Synthesis, ReRAM, and FeRAM","authors":"Pai-Ying Liao, M. Si, G. Qiu, P. Ye","doi":"10.1109/DRC.2018.8442257","DOIUrl":null,"url":null,"abstract":"2D ferroelectric-gated field-effect transistors are promising for future non-volatile memory and low-power logic applications, to combine the advantage of both 2D semiconductors and ferroelectric insulators [1]–[3]. However, the non-ideal 2D semiconductor/3D insulator interface results in interface traps which degrade the device performance, variability and reliability. To integrate 2D semiconductor together with 2D ferroelectric insulator as 2D van der Waals heterostructure ferroelectric field-effect transistors (Fe-FETs) can eliminate the interface trap issue and achieve ideal insulator/semiconductor interface in principle. Copper indium thiophosphate $(\\mathrm{CuInP}_{2}\\mathrm{S}_{6}$, CIPS) is a novel two-dimensional (2D) ferroelectric material with layered single crystal structure and decent ambient stability [4]–[6]. Furthermore, it illustrates not only clear room temperature ferroelectric property with Curie point around 315 K, but also ferroelectric resistive switching characteristic.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 76th Device Research Conference (DRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2018.8442257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

2D ferroelectric-gated field-effect transistors are promising for future non-volatile memory and low-power logic applications, to combine the advantage of both 2D semiconductors and ferroelectric insulators [1]–[3]. However, the non-ideal 2D semiconductor/3D insulator interface results in interface traps which degrade the device performance, variability and reliability. To integrate 2D semiconductor together with 2D ferroelectric insulator as 2D van der Waals heterostructure ferroelectric field-effect transistors (Fe-FETs) can eliminate the interface trap issue and achieve ideal insulator/semiconductor interface in principle. Copper indium thiophosphate $(\mathrm{CuInP}_{2}\mathrm{S}_{6}$, CIPS) is a novel two-dimensional (2D) ferroelectric material with layered single crystal structure and decent ambient stability [4]–[6]. Furthermore, it illustrates not only clear room temperature ferroelectric property with Curie point around 315 K, but also ferroelectric resistive switching characteristic.
二维铁电$\pmb{\mathrm{CuInP}_{2}}\mathrm{S}_{6}}$:合成、ReRAM和FeRAM
二维铁电门控场效应晶体管结合了二维半导体和铁电绝缘体的优势[1]-[3],在未来的非易失性存储器和低功耗逻辑应用中前景广阔。然而,非理想的2D半导体/3D绝缘体界面会导致界面陷阱,从而降低器件的性能、可变性和可靠性。将二维半导体与二维铁电绝缘体集成为二维范德华异质结构铁电场效应晶体管(fe - fet),原则上可以消除界面陷阱问题,实现理想的绝缘体/半导体界面。硫代磷酸铜铟$(\ mathm {CuInP}_{2}\ mathm {S}_{6}$, CIPS)是一种新型的二维(2D)铁电材料,具有层状单晶结构和良好的环境稳定性[4]-[6]。此外,它不仅具有明确的室温铁电特性,居里点在315 K左右,而且具有铁电电阻开关特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信