An Efficient Resource Planning For Semiconductor Manufacturing Lines Using Precise Simulation

Abstract

The large investment required for ASIC manufacturing lines makes it essential to minimize the turnaround time and work-in-process while improving machine utilization. For this purpose, we propose efficient planning method using lot capacity analysis models to estimate the rough numbers of each machine and discrete-event simulation that can reflect many details of actual lot processing and line operation. This paper describes how this can be used to optimize resources in the product mix with some special lot processing.