A novel method to optimum test-nodes selection in analog-circuit fault diagnosis

Abstract

This paper proposes a novel test-nodes selection procedure for parametric fault diagnosis in analog circuit. In this procedure, one considers the impedance value as the most important circuit parameter in fault diagnosis, and establish a closed-form function between circuit impedance and voltage phasor. Such this closed-form function is presented through a few critical faulty voltage phasor response measurements, with which the ambiguous component group can be located. Then the problem of test-nodes selection means to increase testable components number and decrease ambiguous fault-pairs. The automation of the test-nodes selection is tested in an analog circuit benchmark with a bipartite modeling based on fault pair isolation table. The result shows that the proposed test-nodes selection (TNS) procedure is indeed to minimize the size of the test-nodes set, being in the comparison to the exhaustive method.