Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers

Abstract

We report on three-dimensionally (3D) integrated circuits and stacked CMOS image sensors by using the direct bonding of silicon-on-insulator (SOI) layers. Since the developed process allows small embedded Au electrodes by damascene process, high-density integration is possible within an image sensor pixel area of a few micrometers, beyond the limit of the conventional technique such as through silicon vias (TSVs). We confirmed a successful operation of the developed 3D integrated circuits with NFETs and PFETs bonded from separate wafers. We also demonstrated stacked CMOS image sensor with pixel-wise 3D integration, which indicates that our technology is promising for high-density integrated circuits and CMOS image sensors.