On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

Abstract

A fully configurable and synthesizable timing characterization test-bench for memory IPs enables high resolution clk2q, setup, hold and cycle-time delay measurements. The timing test-bench features distributed regional capture FFs, mesh based low-skew clock and setup difference measurement across regional capture FFs to minimize error, multiple data/input delay generators to handle timing permutations across memory inputs, automated relative placement/pre-routing for matched layout and XORed clock delay generators to create multiple edges for measuring read after write delay/cycle time.