Effect of selective tungsten contact fills on manufacturing issues

R. Blumenthal, B. Alburn
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引用次数: 0

Abstract

Summary form only given. The selective deposition of CVD tungsten has been extensively studied as a promising technique for filling contacts and vias in semiconductor devices. The immediate need to apply this technology to devices with submicron contacts and vias requires that consideration be given to defect density, probe yield, process yield, and manufacturability. In addition, process control reliability must also be addressed. The authors show the yield effect of selective tungsten deposition as compared to a standard process flow. The 256 K DRAM was chosen as the test vehicle for the study. The most strongly affected electrical parameters were the contact resistances. In some cases degradation was bad enough to cause continuity failure in the functional tests. Across-wafer uniformities and failure analysis results for the different processes are also reported.<>
选择性钨接触填料对制造问题的影响
只提供摘要形式。CVD钨的选择性沉积作为填补半导体器件触点和过孔的一种很有前途的技术已经得到了广泛的研究。将该技术应用于亚微米触点和通孔器件的迫切需求要求考虑缺陷密度、探头良率、工艺良率和可制造性。此外,还必须解决过程控制可靠性问题。与标准工艺流程相比,作者展示了选择性钨沉积的良率效应。选择256k DRAM作为研究的试验载体。受影响最大的电气参数是接触电阻。在某些情况下,退化严重到足以导致功能测试中的连续性失败。还报告了不同工艺的晶圆均匀性和失效分析结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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