Nanoparticle floating gate flash memories

Abstract

This work presents the use of SiGe nanoparticle floating gates on high-k gate tunneling dielectrics, which, along with SiGe cold cathodes in the channel, are ways to enhance the low voltage/power operation of flash cells, improve the speed and charge retention. Control of dot sizes and spatial distributions may be improved by templated growth. Instead of an array of nanoparticles, it is also possible to use single quantum dots, and exploit Coulomb blockade and multi-level storage in single electron/few electron charge memories, but such devices are susceptible to background charges. It is possible to envision vertical cell structures in a cross-point array at the intersections of the wordlines and bitlines, which can result in an ideal 4F/sup 2/ architecture.