A High Resolution Multibit Sigma-delta Modulator With Individual Level Averaging

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586236

Feng Chen, B. Leung

引用次数: 128

Abstract

A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 /spl mu/m CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 kHz baseband. No tone is observed in the baseband as the amplitude of a 10 kHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm/sup 2/ and it dissipates 67.5 mW of power from a 5 V supply. >

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具有独立电平平均的高分辨率多比特σ - δ调制器

采用单电平平均技术，设计并实现了一种具有3-b内量化器的二阶σ - δ调制器，该调制器采用1.2 /spl mu/m的CMOS技术。测试结果表明，在噪声底之上没有观察到谐波失真分量。在20 kHz基带下，时钟频率为2.56 MHz，峰值S/(N+D)比为91 dB，动态范围为96 dB。在基带中没有观察到音调，因为10khz输入正弦波的幅度从低于参考电压的-0.5 dB降低到-107 dB。原型芯片的有效面积为3.1 mm/sup /，它从5v电源消耗67.5 mW的功率。>

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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