Implementation of full jitter performance test in high-speed serial links with ATE

Abstract

To quantify the transmission quality of HSIO efficiently and accurately is a big challenge in front of SoC ATE test engineers. The common BIST loopback method is easy to setup and time-saving but can not promise an acceptable confidence level for current faster and faster high-speed devices. On the other hand, to fully measure jitter related specs with industry standard instruments will lead to excessive cost of test (e.g., capital investment, time-to-market, test time). This paper proposes one solution for at-speed jitter performance testing on ATE, which covers jitter histogram, random jitter/deterministic jitter separation and jitter spectrum decomposition (stardust). This solution has been implemented in production of real devices and the result shows its high accuracy and cost effectiveness.