Digital-LDO Switched Capacitors based for 0.5V applications

Abstract

This work presents the design of a 0.5V digital low dropout voltage regulator (DLDO) in 180nm CMOS technology for Dynamic Voltage Scaling applications. Dynamic and leakage power consumption in VLSI systems are effectively reduced by ultra-low voltage operation, being that the maximum energy efficiency is achieved at supply voltage below 0.5V. Feedback-controlled analog LDO based on an operational amplifier can fail if it operates at sub/near-threshold voltage. Digital LDOs have potential to replace the analog circuits in the feedback loop for a digital equivalent, which enables ultra-low voltage operation. An efficiency peak of 98%, an steady-state error lower than 7mVp was achieved by post-layout simulations for a load current range from 100μA to 1.25mA.