Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation

Abstract

This paper presents Read Margin analysis for large SRAM arrays with a fast test method that even can be realized in dual-VDD product chips. Classical Static Noise Margin (SNM) is mostly suitable for single-cell simulation. Read Margin (RM) measurement allows analysis of large arrays and correlates to SNM, but requires a dedicated teststructure and long measurement time. The presented method analyzes the flipping of cells over varying supply voltage. The stability of large arrays can be characterized in read as well as in hold state depending on the state of the access transistors. Applying this method, the impact of Negative Bias Temperature Instability (NBTI) is demonstrated on both Read and Hold Margin in a 65 nm low power technology.