Triple level polysilicon E2PROM with single transistor per bit

J. Kupec, W. Gosney, V. McKenny, V. Kowshik
{"title":"Triple level polysilicon E2PROM with single transistor per bit","authors":"J. Kupec, W. Gosney, V. McKenny, V. Kowshik","doi":"10.1109/IEDM.1980.189905","DOIUrl":null,"url":null,"abstract":"An electrically-erasable, floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROMS. Erasure is accomplished with the third level of polysilicon which serves as an erase electrode causing field emission of electrons from the edges of the floating-gate. Conventional NMOS processing is used and all oxides are thicker than 800A. An adaptive erase feature is used to prevent over erasure into depletion and eliminates the requirement of a gating or series enhancement transistor. Endurance (ability to program and erase repeatedly), of a single cell is greater than 1000 cycles and is limited by electron trapping. Data retention has been experimentally determined to be comparable to EPROMs (greater than 10 years).","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189905","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

An electrically-erasable, floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROMS. Erasure is accomplished with the third level of polysilicon which serves as an erase electrode causing field emission of electrons from the edges of the floating-gate. Conventional NMOS processing is used and all oxides are thicker than 800A. An adaptive erase feature is used to prevent over erasure into depletion and eliminates the requirement of a gating or series enhancement transistor. Endurance (ability to program and erase repeatedly), of a single cell is greater than 1000 cycles and is limited by electron trapping. Data retention has been experimentally determined to be comparable to EPROMs (greater than 10 years).
三能级多晶硅E2PROM,每位单晶体管
描述了一种利用三层多晶硅的可电擦除的浮栅PROM电池。该细胞通过类似eprom的通道注入机制进行编程。擦除是用第三层多晶硅完成的,该多晶硅作为擦除电极,引起从浮栅边缘发出电子的场发射。采用传统的NMOS工艺,所有氧化物厚度均大于800A。自适应擦除特性用于防止过度擦除到耗尽,并且消除了对门控或串联增强晶体管的要求。单个电池的寿命(重复编程和擦除的能力)大于1000次循环,并受到电子捕获的限制。数据保留已被实验确定可与eprom相媲美(大于10年)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信