Reduction of extrinsic base-collector capacitance in InP/InGaAs SHBTs using a new base pad design

Abstract

A method to isolate the base pad from the intrinsic device structure for reducing the extrinsic base-collector capacitance of InP/InGaAs single heterojunction bipolar transistors(SHBTs) is reported, which uses a new base pad layout. The new layout is designed based on the lateral etching characteristics of an InGaAs collector layer with different crystal orientations. The new layout allows more effective and easier base pad isolation for InP-based HBTs, which have the emitter aligned to [011] or [011~] directions, without excessive lateral or additional etching. The maximum f/sub T/ and f/sub max/ of the fabricated device with a 2 /spl times/ 10 /spl mu/m/sup 2/ emitter size using the new layout were found to be 72 and 242 GHz, respectively.