Statistical measurements and Monte-Carlo simulations of DCR in SPADs

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI:10.1109/ESSCIRC55480.2022.9911519

Mathieu Sicre, M. Agnew, C. Buj, C. Coutier, D. Golanski, R. Helleboid, B. Mamdy, I. Nicholson, S. Pellegrini, D. Rideau, D. Roy, F. Calmon

{"title":"Statistical measurements and Monte-Carlo simulations of DCR in SPADs","authors":"Mathieu Sicre, M. Agnew, C. Buj, C. Coutier, D. Golanski, R. Helleboid, B. Mamdy, I. Nicholson, S. Pellegrini, D. Rideau, D. Roy, F. Calmon","doi":"10.1109/ESSCIRC55480.2022.9911519","DOIUrl":null,"url":null,"abstract":"Dark Count Rate (DCR) in 3D-stacked CMOS Single-Photon Avalanche Diode (SPAD) is investigated by means of measurements and simulations at various temperatures and voltages. This study strengthens previous hypotheses on the roles of depleted regions and interfaces in DCR generation by examining device architectures. A nonradiative multiphonon-assisted trapping model (NRM) is used to calculate the carrier capture/emission rate of defect sites. Systematic comparison between measurement and Empirical Monte-Carlo (EMC) simulation, accounting for the stochastic diffusion of carriers in computation of the avalanche breakdown probability (Pt), was performed to investigate trap and avalanche positions within the device. This simulation unveils device regions contributing to different DCR dynamics by de-embedding carrier avalanche localizations. Based on this simulation methodology, the DCR statistical distribution induced by local device-to-device process variation is covered by randomly setting the defect positions and sizes within the device.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911519","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

Abstract

Dark Count Rate (DCR) in 3D-stacked CMOS Single-Photon Avalanche Diode (SPAD) is investigated by means of measurements and simulations at various temperatures and voltages. This study strengthens previous hypotheses on the roles of depleted regions and interfaces in DCR generation by examining device architectures. A nonradiative multiphonon-assisted trapping model (NRM) is used to calculate the carrier capture/emission rate of defect sites. Systematic comparison between measurement and Empirical Monte-Carlo (EMC) simulation, accounting for the stochastic diffusion of carriers in computation of the avalanche breakdown probability (Pt), was performed to investigate trap and avalanche positions within the device. This simulation unveils device regions contributing to different DCR dynamics by de-embedding carrier avalanche localizations. Based on this simulation methodology, the DCR statistical distribution induced by local device-to-device process variation is covered by randomly setting the defect positions and sizes within the device.

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spad中DCR的统计测量和蒙特卡罗模拟

通过测量和仿真，研究了三维堆叠CMOS单光子雪崩二极管(SPAD)在不同温度和电压下的暗计数率(DCR)。本研究通过检查器件架构加强了先前关于耗尽区域和接口在DCR生成中的作用的假设。采用非辐射多声子辅助俘获模型(NRM)计算缺陷位点的载流子俘获/发射率。在雪崩击穿概率(Pt)计算中，考虑载流子的随机扩散，对测量和经验蒙特卡罗(EMC)模拟进行了系统比较，以研究器件内的陷阱和雪崩位置。该仿真揭示了通过去嵌入载波雪崩定位对不同DCR动态做出贡献的器件区域。基于该仿真方法，通过随机设置器件内缺陷的位置和尺寸，覆盖器件间工艺变化引起的局部DCR统计分布。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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