FPGA core PDN design optimization

Abstract

This paper analyses and quantifies the impact of numbers of package power and ground balls and on-package decoupling capacitors (OPD) on an FPGA's on-chip core power distribution network (PDN) performance. Measurement methodologies are developed to study the PDN quality in both time domain and frequency domain. The PDN performance is evaluated from three aspects, the PDN noise amplitude, core logic maximum operation frequency, and system clock jitter. The findings help chip designers optimize the PDN design to achieve a cost and performance balance.