Modeling of Data Delivery Modes of Next Generation SOC-NOC Router

Abstract

As technology is advancing the size of the computational devices are reducing. As a result, the integration of number of processing elements is increasing on the System on Chip (SoC). As the device size is reduced the gate delay will also get reduced, this intern increases the frequency of operation of the devices. Conventional on-chip router architectures used bus based infrastructure, which was point to point communication were not able to communicate suitably due to the increase in the frequency of operation in SoCs. These communication systems used for on-chip communication are not scalable and does not support design reuse.So, the NoC was introduced to provide scalability and flexibility for on-chip communication for the Multicore processors. This research paper has an objective of development of next generation multi-functional Network on Chip router architecture. This paper also covers the system design & simulation of multi-functional router under various data delivery modes, with an intension to implement all of them on FPGA. The modules of data delivery modes are designed using Verilog HDL.